00997nam a2200193 c 4500001001300000005001500013007000300028008004100031040001100072041001300083052003900096245016900135300002600304545010700330653013600437700005300573773015900626900001800785KSI00085511020110708142030ta110504s1999    ulk           000   kor    a0110010 akorbeng01a560.5b대483ㄱㄱc48(10)-48(12)00aCMOS 디지털 게이트의 최대소모전력 예측 매크로 모델 =xMacro-model for estimation of maximum power dissipation of CMOS digital gates /d金東郁  ap. 1317-1326 ;c30 cm  a김동욱, 정회원, 광운대 전자재료공학과 부교수·공박bvlsicad@daisy.kwangwoon.ac.kr  aMaximum power estimationaMacro modelaMOSFET characteristicsaCMOS logic gateaRelative error ratea입력신호a전력 민감도1 a김동욱,g金東郁,d1960-0KAC2017422334aut0 t전기학회논문지. A, 전력기술부문.d대한전기학회.g48권 10호(1999년 10월), p. 1317-1326q48:10<1317w(011001)KSE199900352,x1229-244310aKim, Dongwook