01070nam a2200205 c 4500001001300000005001500013007000300028008004100031040001100072041001300083052003800096245018700134300002500321545009900346653017600445700005300621773014700674856002000821900002300841KSI00075756920090827161918ta090525s2007    ulk           000   kor    a0110010 akorbeng01a004.05b한613ㅈㅂc14(1)-14(3)00aReed-Muller 전개식에 의한 다치 논리회로의 구성에 관한 연구 =xStudy on construction of multiple-valued logic circuits based on Reed-Muller expansions /d성현경  ap. 107-116 ;c30 ㎝  a성현경, 종신회원, 상지대학교 컴퓨터정보공학부 교수bhkseong@sangji.ac.kr  a다치논리회로aKronecker 곱aPerfect shufflea다치 Reed-Muller 전개식aMultiple-valued logic circuitsaKronecker productaMultiple-valued Reed-Muller expansions1 a성현경,g成賢慶,d1955-0KAC2018043564aut0 t정보처리학회논문지. A.d한국정보처리학회.g14-A권 2호(2007년 4월), p. 107-116q14:2<107w(011001)KSE200101428,x1598-283140uT00000576502ad10aSeong, Hyeonkyeong