01091nam a2200229 c 4500001001300000005001500013007000300028008004100031040001100072041001300083052003500096245014600131300002200277545009000299545008700389653007500476700005300551700004800604773017000652900001900822900002000841KSI00073070820081209134917ta081203s2002    ulk           000   kor    a0110010 akorbeng01a569.9305b제567ㅈc8(1)-8(3)00aFPGA 구현을 통한 자이로의 혼합모드 연구 =x(A)study on the mixed mode of gyros by FPGA implementation /d노영환,e방효충  ap. 54-59 ;c30 cm  a노영환, 우송대학교 컴퓨터·전자정보공학부byhlho@lion.woosong.ac.kr  a방효충, 한국과학기술원 항공우주공학전공bhcbang@fdcl.kaist.ac.kr  aFPGAaGyroaBitaUp/down counteraFPGA 구현a자이로a혼합모드1 a노영환,g盧泳煥,d1954-0KAC2017090384aut1 a방효충,g方孝忠,d1964-0KAC2016222450 t제어·자동화·시스템공학 논문지.d제어·자동화·시스템공학회.g제8권 1호(2002년 1월), p. 54-59q8:1<54w(011001)KSE199900457,x1225-984510aLho, Younghwan10aBang, Hyochoong