00882nam a2200205 k 4500001001500000005001500015008004100030049001700071052001900088056001400107082001600121100005100137245016000188260003600348300003200384502008100416653012800497900003100625963002000656KDM199840025  20201008101014990222s1998    ulka       AK 000   eng  0 lWM254359fDP02a621.395bW394m  a569.47240 a621.3952211 a위재경,g魏在慶d1966-20150KAC20170234710aModeling and characterization of multi-layered interconnects in VLSI circuits=xVLSI 회로에서 다층 연결선의 모델링과 특성분석/d魏在慶  a서울:b서울大學校,c1998  axvii, 161 p.:bill.;c26 cm1 a학위논문(박사) --b서울대학교 대학원:c전자공학과,d1998.  aMODELINGaCHARACTERIZATIONaMULTILAYEREDaINTERCONNECTSaVLSIaCIRCUITSa회로a다층a연결선a모델링a특성분석10aWee, Jae-kyung,d1966-2015  a전자공학과